CSE467 Laboratory Assignment 2: XCV1000 and Verilog UART
Distributed: January 11, 2005
Due start of next lab session

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Objectives

In Part I of this laboratory assignment you get to know the technique for creating and running a verilog program for the XCV1000.

In Part II we will implement an RS-232 interface between your lab PC and the XCV1000. You will implement a UART in verilog, and echo the serial data back to your PC.

In Part III you will add a buffer for a string of serial data.

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Part I. Compiling and Programming for XCV1000bg560

Create a workspace

• Open Active HDL
• Select the option to create a new workspace
• Enter your workspace name and change the location of your workspace folder
• The path to the workspace cannot have any spaces in it 
• Do not save on the lab machines hard drive: they will get erased when you log off
• Press OK.  Active HDL will create your new workspace
• Check the Add existing resource files bullet
• Click Next
• Click Add Files…
• Use Flash_LED.v
• Click Next
• Set the options for the New Design Wizard as shown in Figure 1 and hit Next
• Enter your design name, click Next and Finish

 

Figure 1

 

Synthesize

• Select the design flow window
• Select synthesis options
• Select the highest level verilog in the Top-Level Unit box
• Change the Family to Xilinx6x VIRTEX
• Change the Device to V1000bg560, the V1000 part in the Ball grid array package
• Change the Run Mode to GUI
• Press ok, and press the Synthesize button
• Press Run after Synplicity opens up
• (If you're on a subsequent pass through here, Impact and Synplify conflict, so exit from Impact.)
• After a few seconds, if everything goes right, it will display Done!
• Synpliclty is a very useful tool if you know how to use it
• Click the View Log button on the left-hand side of the screen to view a detailed timing report
• You can see how your design is laid out in two different views
• From the HDL Analyst menu, select RTL > Hierarchical View  
• From the HDL Analyst menu, select Technology > Hierarchical View
• After you spend a little time playing with Synplicity, close out of it
• Press the refresh file list button
• Hit the “…” button to the right of Netlist:
• Select the current .edf file and hit Open then Ok
• The question mark next to the Synthesis button should now be a green check

 

Implement

• Save Generic_Pin_List.ucf in your design folder
• Select options, to the left of implementation.
• Change the Run Mode to Batch
• Select the Translate tab
• Deselect Use default UCF file
• Press the Browse  button on the top right
• Select the Generic_Pin_List.ucf file and press Open
• Next, select the Timing and Configure tab
• Change the Simulation Output Format to None
• Check the Generate Bit File bullet
• Press OK
• Press Implementation
• You should have no errors; you may have some warnings.
• Close the implementation window when it finishes

Program

• Click on the Analysis button and open iMPACT
• Check the parallel cables and make sure your FPGA is plugged in and powered up
• The light on the programmer will be green if everything is okay
• iMPACT will eventually start up, and present you with a wizard
• Select Configure Devices, then Next.
• Select Slave Serial Mode, then Finish.
• An Add Device window will pop up.
• You need to choose the .bit design file, which is located in: <design_name>\implement\ver1\rev1\
• Press Open
• An icon representing your design will appear.
• Right-click the icon and click on Program…
• If everything went right, iMPACT will display Programming Succeeded.
• The Done led on the Xilinx board should be lit and the AJ2 led should be flashing

Modify the program

• Variant 1: Modify the verilog code to change the blink rate.
• Variant 2: Modify the verilog code to blink a two-three pattern: blink, blink, off, blink, blink, blink, off.. 

Editing the Pin Constraints

• Before you can program the FPGA with any additional implementations, you need to update the pin constraints file
• You can edit the Generic_Pin_List.ucf file with any text editor
• The file already contains all of the pins that are available for input/output on the XCV1000
• You will need to assign a free pin to all of the input and outputs you have defined in your top-most module
• XCV1000-Pin-Layout has a graphical display of the XCV1000’s pins

Check off: demonstrate your two-three pattern to the TA.

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Part II. Serial Interface in verilog

Serial Echo Project

There are two basic pieces to this project.  The first is the SerialUart.v, which is the module that we will provide to you.  The second is the SerialCtrl.v module, which is the module you will be required to modify.  All this project does is read characters that are typed into hyperterminal and echo the characters back to hyper-terminal one at a time.

SerialUart Module

This module uses the serial uart modules from opencores.org.  We wrote this module as a wrapper to combine all the modules that are needed for the uart to function like a standard serial uart.  The data goes into and comes out of this module through transmit and receiver FIFOs.

Here is a short description of each i/o port:

Clk: The standard 50 MHz global clock input.

Reset: The standard active-high reset input.

RX: The receive input from the RS-232 chip.  This pin needs to be included in the ucf file.

TX: The transmit output to the RS-232 chip.  This pin needs to be included in the ucf file.

Read_RX_FIFO: Control signal input that should be set high to read from the fifo.

Write_TX_FIFO: Control signal input that should be set high to write into the fifo.

TX_Buffer_Full: Transmit fifo status signal which means you can’t write a value into the fifo.

RX_Data_Present: Receive fifo status signal which tells you when data has been received.

TX_Data: The 8-bit data input which you write to when sending data.

RX_Data: The 8-bit data output which you read data from when receiving.

The serial uart has one receive and one send fifo.  Each of them is a four-deep fifo.

A few things to note about timing: First, both the Read_RX_FIFO and Write_TX_FIFO control signals should only be set high for one clock cycle.  If they are held high for longer than that, they will read or write multiple values.  When transmitting data, the register which the TX_Data is wired to needs to have its value present before Write_TX_FIFO is pulsed high because the SerialUart module latches the data in TX_Data when Write_TX_FIFO goes high.  When receiving data, it is okay to latch the data from RX_Data as soon as the RX_Data_Present signal goes high. 

SerialCtrl Module

This module instantiates the SerialUart module and goes into a listen state.  When the RX_Data_Present signal goes high, it latches the data from RX_Data, writes it into a send register, which is wired to the TX_Data, and then drives the Write_TX_FIFO high for one clock-cycle.  There is not really a need to check the TX_Buffer_Full signal before writing because it’s receiving data at the same rate that it is writing data. We have provided a simple versionof the module; you must modify and improve this module to complete this section of the lab.

To do:

First, wire your RS-232 interface according to this schematic:

Hint: place this circuit at the UPPER END OF THE PROTO AREA, CLOSEST TO THE POWER CONNECTIONS. You will need the space for next week's lab.

You will find the correct pins to connect RX and TX in the serialecho.ucf file below.

Next, create a new workspace in ActiveHDL as in part I above, and add the following files to it:

serialuart.v
serial_ctrl.v
serialecho.ucf

serial_cntl.v is the module you must modify. You must change the state machine to detect a carraige return (ENTER key) and send a carraige return/line feed pair to hyperterminal. Hint: You may need to add a state to the state machine. (see serial_cntl2.v below for hints on detecting a carraige return.)

The ucf file is similar to the Generic_Pin_List.ucf file in part I, and should be used in an identical manner. Follow the procedures in Part I to compile and load your verilog. Plug your DB9M into the com1 serial cable from your lab PC, and use hyperterminal for testing. To run hyperterminal, go " Start -> Accessories-> Communications -> hyperterminal".

The baudrate needs to be set to 57600 bits/sec and the flow control should be set to none.

Check off: demonstrate your improved character-echo to the TA.

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Part III. Serial String buffering in verilog

Serial String Project

Create a new workspace in ActiveHDL as in part I above, and add the following files to it:

serial_ctrl2.v
serialuart.v
serialecho.ucf

This project has all of the same components as the serial echo project.  The functionality of the SerialCtrl2 module is slightly different.  Rather than reading and writing one character at a time, a whole string of characters are read in from hyper-terminal and then written back when the ‘ENTER’ key is pressed. 

To accommodate this, there is an internal memory which data is written into as it is read from the uart.  Each time a new character is read, the serial controller checks to see if it is the ‘ENTER’ character.  If it’s not, the new value is written to serial_buffer and the memory pointer is incremented.  If it does match the ‘Enter’ character, the memory pointer is reset to 0 and all the values stored in serial_buffer are transmitted back to the hyper-terminal.  Since, it is possible to write characters faster than they can be transmitted, it is important to check the TX_Buffer_Full signal before writing to the TX fifo.

The SerialCtrl2 module has the same problem that SerialCntl had.. Your job is to improve it in a similar manner to part II above, so that it adds a line feed when an ENTER (carraige return) is detected. Hint: You may need to add a state to the state machine.

Check off: demonstrate your improved buffered character-echo to the TA.

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bruceh@cs.