`timescale 1 ns / 1 ps module serial_ctrl ( RX ,Clk ,Reset ,TX, RX_Data_Present, debug ); input RX ; wire RX ; input Clk ; wire Clk ; input Reset ; wire Reset ; output TX ; wire TX ; output RX_Data_Present; output [7:0] debug; wire [7:0] debug; parameter S_0 = 2'b00, S_1 = 2'b01, S_2 = 2'b10, S_3 = 2'b11; wire Write_TX_FIFO; wire [7:0] TX_Data; wire TX_Buffer_Full; wire Read_RX_FIFO; wire [7:0] RX_Data; wire RX_Data_Present; wire [7:0] send_data; reg [7:0] rcvd_data; reg [1:0] state, next_state; SerialUart uart_mod( Clk, Reset, RX, TX, Read_RX_FIFO, Write_TX_FIFO, TX_Buffer_Full, RX_Data_Present, TX_Data, RX_Data ); assign send_data = (state == S_2) ? RX_Data : rcvd_data; assign Read_RX_FIFO = (state == S_2) ? 1: 0; assign Write_TX_FIFO = ((state == S_3) && (TX_Buffer_Full == 0))? 1: 0; assign TX_Data = rcvd_data; assign debug = rcvd_data; always@(posedge Clk) begin if(Reset == 1) state <= S_0; else begin state <= next_state; rcvd_data <= send_data; end end always@(state,RX_Data_Present,send_data) begin next_state = state; case(state) S_0: next_state = S_1; S_1: if(RX_Data_Present) next_state = S_2; S_2: next_state = S_3; S_3: next_state = S_1; default: next_state = S_0; endcase end endmodule