We will be using Active-HDL from Aldec
Inc. This tool combines schematics, the Verilog harware
description language and simulation into one package. This tool will
allow us to design at different levels of abstraction and interfaces to
a variety of implementation tools for FPGAs and ASICs. Many of you have used this tool in 370.
As a refresher, please review these tutorials.
Active-HDL Tutorial 1 Creating and Simulating Simple Schematics (pdf version)
Active-HDL Tutorial 2 Hierarchical Designs and Test Fixtures (pdf version)
Active-HDL Tutorial 3 Introduction to Using Verilog in Active-HDL (pdf version)
We won't check whether you did this work-- but we'll know soon enough!