CSE467 Homework 3

Distributed: January 21, 2005
Due: Start of Class, January 28, 2005

Design:

1. In class, we went through one way of designing of a run-length encoder (RLE). In this problem, we will implement the other version of run-length encoding. Specifically:
   
1. Characters that appear singly or in pairs are simply copied to the output stream (possibly with some delay).
2. Runs of 3 or more characters are replaced by three characters:
   character, 255, count-3

This assumes that the character 255 never occurs. You may also assume that runs of more than 258 characters never occur. The input character will be 8-bits and the output character must be 8-bits. Your output stream must, of course, use the dataValid signal. The input also should take a dataValid signal that signifies a valid input stream.

• Draw a high-level schematic of your design’s datapath (registers, ports, and logic blocks).
• Draw a state diagram for the control part of your design.
• Implement this design using Verilog (two always blocks!).
• Verify that your design works using the test fixture that we provide. Use ClockGen from lib370 for the clock and reset signals.

Turn in your drawings, Verilog code, and your console output from the test fixture (don’t print out more than a couple pages).

1. In Lab 2 we used a verilog serial uart. We want you to examine serialuart.v from that lab, and answer the following questions:
   
   1. What is a DPLL (Digital Phase Lock Loop), and how does the DPLL FSM work?
   2. What is the function of the Edge Detector code, and how does it work?
   3. Where does the 4x baud clock come from?
   4. How is the start bit detected?
      
   Keep your answers short and to the point. Hand in no more than a two pages, NOT handwritten.