Moore Verilog FSM (cont’d)
always @(in or state) case (state)
zero: begin // last input was a zero out = 0; if (in) next_state = one1; else next_state = zero; end
one1: begin // we've seen one 1 out = 0; if (in) next_state = two1s; else next_state = zero; end
two1s: begin // we've seen at least 2 ones out = 1; if (in) next_state = two1s; else next_state = zero; end
default: begin // in case we reach a bad state
crucial to include all signals that are input to state and output equations