Shift Register Example
// 8-bit register can be cleared, loaded, shifted left
// Retains value is no control signal is asserted
module shiftReg (CLK, clr, shift, ld, Din, SI, Dout);
input clr; // clear register
input ld; // load register from Din
input [7:0] Din; // Data input for load
input SI; // Input bit to shift in
always @(posedge CLK) begin
else if (ld) Dout <= Din;
else if (shift) Dout <= { Dout[6:0], SI };