Verilog for
for statement is executed at compile time
- result is all that matters, not how result is calculated
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment
integer i; // Temporary variables for program only
for (i = 0; i < 8; i = i + 1) begin