Simple Behavioral Model - the always block

module and_gate (out, in1, in2); input in1, in2; output out; reg out; always @(in1 or in2) begin

out = in1 & in2;

end

endmodule

• always block

  • always waiting for a change to a trigger signal
  • then executes the body

Not a real register!!

A Verilog register

Needed because of

assignment in always block

specifies when block is executed ie. triggered by which signals

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