Other Types of Latches and Flip-Flops
Best choice is D-FF simplest design technique, minimizes number of wires preferred in PLDs and FPGAs good choice for data storage register edge-triggered has most straightforward timing constraints
Historically J-K FF was popular versatile building block, usually requires least amount of logic to implement function two inputs require more wiring and logic (e.g., two two-level logic blocks in PLDs) good in days of TTL/SSI, not a good choice for PLDs and FPGAs can always be implemented using D-FF
Level-sensitive latches in special circumstances popular in VLSI because they can be made very small (4 transistors) fundamental building block of all other flip-flop types two latches make a D-FF
Preset and clear inputs are highly desirable