Clock Skew
Correct behavior assumes that all storage elements sample at exactly the same time
Not possible in real systems:
- clock driven from some central location
- different wire delay to different points in the circuit
Problems arise if skew is of the same order as FF contamination delay
Gets worse as systems get faster (wires don't improve as fast)
- 1) distribute clock signals in general direction of data flow
- 2) wire carrying the clock between two communicating components should be as short as possible
- 3) try to make all wires from the clock generator be the same length – clock tree