Systolic Architectures

• Highly parallel

  • “fine-grained” parallelism
  • deep pipelining

• Local communication

  • wires are short - no global communication (except CLK)
    • linear array ? no clock skew
  • increasingly important as wire delays increase (relative to gate delays)

• Linear arrays

  • most systolic algorithms can be done with a linear array
  • include memory in each cell in the array
  • linear array a better match to I/O limitations

• Contrast to superscalar and vector architectures

Previous slide

Next slide

Back to first slide

View graphic version