Computer-aided Design
Can't design FPGAs by hand
- way too much logic to manage, hard to make changes
Hardware description languages
- specify functionality of logic at a high level
Validation - high-level simulation to catch specification errors
- verify pin-outs and connections to other system components
- low-level to verify mapping and check performance
Logic synthesis
- process of compiling HDL program into logic gates and flip-flops
Technology mapping
- map the logic onto elements available in the implementation technology (LUTs for Xilinx FPGAs)