To test your implementation you'll need to initialize the various memories at some point. This page describes the tools we've created to make this process less painful. It also provides a running example that you can follow. In order to follow this example, you'll need to download the following files:
Include these files in your design, making sure that you check the "make local copy" box.
To initialize your instruction ROM, you should do the following things the first time:
open make_rom.do
replace $3 with the name of your ROM followed by ".INIT_C%d".
As an example, assume your instruction rom is named IROM. Then the line
would look like this:
runscript asm_to_hex.pl -in=$1 -out=$2 -init=ROM -obj=IROM.INIT_C%d
//synopsys translate_off
`include "testrom.rom"
//synopsys translate_on
After you've completed these steps, you need to generate the file
"testrom.rom". The method described here uses a mini-assembler to
convert a subset of mips assembly into the correct hex code, then generates the
correct initialization instructions. In this case, we are trying to generate
"testrom.rom" from a file named "378tester.s" also in the
"src" directory of the current design. So, we type:
do make_rom.do 378tester.s testrom.rom
The final step is to recompile the block diagram that contains the "include" statement. If you don't, the ROM may not be updated properly.
To initialize your Data Ram for LAB1 you should do the following things the first time:
open make_ram.do
replace $3 with the name of your RAM. As an example, assume your instruction rom is named
DMemory. Then the line
would look like this:
runscript asm_to_hex.pl -in=$1 -out=$2 -init=ASYNC -obj=DMemory
//synopsys translate_off
`include "dataram.ram
//synopsys translate_on
After you've completed these steps, you need to generate the file "dataram.ram". To support this, we've defined a simple format for describing memory contents. Here's a quick description of this format:
Here's a quick example to demonstrate this style of memory specification. The following file consists of 3 words at 0,4,8 and the same three words at address 256,260,264.
// Sample data file
0xF9E8D7C6
32'hB5A49382
255
@256
0xF9E8D7C6
32'hB5A49382
255
Now that we've defined this file, the last step is to actually generate the file "dataram.ram". Here's how:
do make_ram.do data.hex dataram.ram
The final step is to recompile the block diagram that contains the "include" statement. If you don't, the RAM may not be updated properly.
Initializing RAM and ROM (Synthesis)
The earlier sections described how to generate and utilize the initialization files during simulation. Unfortunately, these same files can't be used during synthesis, so we need a different method. This method is to use a synthesis design constraint (.sdc) file and notify Synplicity. The first step is generating this file, which we'll do with the script make_sdc.do. One key point is ensuring that you use the correct hierarchical names for your ROM and RAM components. If they are included in your top-level design, then the actual component names should be used. If you have a hierarchy, then be sure to use the whole name (i.e. U1.U7.DRAM).
To create an .sdc file you need to specify 5 arguments: source for
instruction rom, source for data ram, output file, name of rom, and name of ram.
If you have all these, you can simply run the script make_sdc.do in the
following way:
do make_sdc.do strcpy.s data.hex strcpy.sdc IROM DRAM
This will generate a file named strcpy.sdc.
In the design flow window, open the options for the synthesis ( see XUP tutorial ). It should look similar to the one below. For now, we only care about the field name "Constraints File". Use the locate button to find the file strcpy.sdc. At this point, you'll be ready to follow the rest of the XUP tutorial.