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CSE 378 Spring 2006
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How to program the XUP Boards
Step 1: Setting Up a Design in Active HDL
Just like in CSE 370, start up Active HDL and create a new Design with the New Design Wizard. When you come to the Synthesis options, choose “Synplicity
Synplify Pro 8.x” as the Synthesis tool and “Xilinx ISE 7.1” as the Implementation Tool. Set the Default Family to “Xilinx7x VIRTEX2P”.
Pick a design name and complete the process as usual.
Step 2: Design
If you are writing a Verilog file, this step is the same as in CSE 370. If you are using a block diagram, be sure that you are using symbols from the
provided CSE378 Library. Do not use symbols from lib370. We will go into more detail about design in class.
Step 3: Synthesis
Go to the Flow Diagram. Click on Options. Change the device to “2vp30ff896”. Also, switch over to the "Libraries" tab, and add the files that you used from other libraries. To do this, click on "Add Alias", enter a name, and then go to the source files for the library and add them to the list. At this point, leave the rest of the settings alone other than the top level
option (select the item you want synthesized). Click OK once you are done setting things up.
Click Synthesis. Synplify Pro will now launch.
Step 4: Synplify Pro
Once Synplify has launched, you should have a screen like the following:
Click Run. Synplify will now process for a while and then say “Done” when the process is complete. This will create several files. Close Synplify.
Step 5: Implmentation
Go back to ActiveHDL’s Design Flow. Click on the “Refresh file list” button next to “Synthesis”. For Netlist, click the “…” button and go into the folder
with the name of your design and then choose the .edf file. For Simulation File, do the same thing but choose the .vm file.
The question mark by Synthesis should change to a check mark. Click on “Options” by “Implementation” and select “GUI” for Run Mode.
Click “Implementation” to begin the implementation part of the process. This process may take a while. Once it completes, it will launch the “Project
Navigator”
Step 6: Project Navigator
Right click on the name of the project, and select “Add Copy of Source…” and point it at your .ucf file. Double-click on “Configure Device”. Project
Navigator will perform Translation, Mapping, and Placement as it compiles your design. This process may take a while. Once it is complete, you will get a
window. Select “Boundary-Scan Mode” and click Next. Select “Automatically connect to cable…” and click Finish. You will now get a window with 3 chips in it.
Step 7: Programming the Board
You will be asked to assign a new configuration file. While xcf32p is green, click Bypass. When xccace is green, click Bypass again. When xc2vp30 is green,
there should be a file with a .bit extension. Select this file. Click OK. Ignore the warning message.
Right click on xc2vp30 and click “Program…” and click OK.
Congratulations, you have successfully programmed the XUP board. If the process was successful, the “Done” light on the board will turn red.
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Computer Science & Engineering
University of Washington
Box 352350
Seattle, WA 98195-2350
(206) 543-1695 voice, (206) 543-2969 FAX
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