Lab 2: Pipelined MIPS

Description
In this lab, you will build on the single cycle processor that you have designed and make it a 5-stage pipelined processor. We will be following the standard MIPS pipeline implementation, meaning that the processor will have IF, ID, EX, MEM, and WB stages.

In addition to upgrading the processor to a pipelined design, you will no longer be using a ROM to hold your programs on hardware. A new memory system has been designed and will be provided to you so that you can download your programs via the serial cable. This new system will also allow you to control the LEDs and the VGA output, which will be important if you are choosing to go with 378-HW.

Software Stage (Both 378 and 378-HW)
You will have to design a working 5-stage pipelined processor in ActiveHDL, and will write a program that echoes serial input from the serial port back to the machine which sends it. For purposes of simulation, we will provide a simulated serial input and simulated serial output that will allow you to see if your code is working.

Hardware Stage (378-HW only)
You will be implementing your design on the board, and will be using the actual serial interface to download your programs to the board. For this assignment, you will write a program in C/C++ and use a compiler to get the assembly version of your program to send to the board.

The program that you write will be a basic game. You will be able to map buttons to locations in memory and access them to work with your processor. Also, you will be using a VGA module for output to show what is going on in your game.

Design Constraints
We will be sticking to the following constraints to make the lab as straightforward as possible:

Branches and jumps will be followed by a single delay slot containing either an independent instruction or a nop. This will allow us to keep the branch and jump logic in the ID stage.
By the end of the lab, you will have implemented most, if not all of the MIPS instruction set.

New Components
There are four new components that you will be given for this lab:

Memory System
- The memory system integrates the BIOS, IRAM, DRAM, Stack, and IO Management into one module and accepts a data address input and an instruction address input as methods for addressing.
- For purposes of our lab, the ranges of memory are as follows:
  - BIOS: 0x00000000 - 0x003ffff
  - IRAM: 0x00400000 - 0x0fffffff
  - DRAM: 0x1000000 - 0x7ffeffff
  - Stack: 0x7fff0000 - 0x7ffffffff
  - IOControl: 0x80000000 and above
- If the instruction address provided is less than 0x00400000, the instruction is fetched from the BIOS rather than the IRAM.
- Writing to the IRAM is only supported if the BIOS is still running and is the source of instructions.
- The IO Controller takes the address provided and routes it to one of four IO devices. Each IO device receives the lower 5 bits of the address as its command/address, and bits 6 and 5 are used to determine which IO device receives the message. For example, 0x80000000 refers to IO device 0, and provides it the address 0, while 0x80000401 refers to IO device 1 and provides it the address 1.
- The memory system should initialize into the BIOS, and will stay there until you have sent code via the 378 Bootloader software, which will be provided, at which point it will transition into your code and execute it.
- The BIOS for the system assumes that you have connected the serial controller to IO device 0, and the LED controller to IO device 1. You are free to change this if you wish, but you edit the BIOS at your own risk.
- The BIOS will turn on one of the LEDs when it is active, and turn it off once you jump out of the BIOS and into your program.
- To make the SDC file work properly, name the memory system "MemorySystem" in ActiveHDL so that it is clear where the BIOS is located.
Serial Controller
- The serial controller runs at 50 Mhz. Failure to set this clock speed correctly will result in failed program sends.
- The serial controller is used to control dataflow from the serial ports into the system. It can be polled and data can be retrieved it from it by using the appropriate addresses.
- These addresses are as follows (assuming the serial controller is hooked into the IODevice0 ports):
  - 0x80000000 - Returns 1 if there is data waiting to be read
  - 0x80000001 - Returns the 1-byte command code of the data in the buffer
  - 0x80000002 - Checks if there’s room in the send buffer to send data out. Returns 1 if there is room to fit the new data in there.r
  - 0x80000003 - Clear instruction, tells the serial interface to get the next item in the buffer ready for the processor to access it.
  - 0x80000004 - Gets the data that is waiting in the serial recieve buffer
  - 0x80000008 - Store to this address to write a word to the serial transmitter.
VGA Controller
- The VGA Controller consists of two memory-mapped ranges. The VGA configuration we're using has 75 rows and 100 columns.
- The addresses increase from left to right across a row.(i.e. top-left is 0x0000C000 and top-right is 0x0000C063)
- Writing a character means writing the ASCII value to the VGA_TEXT_PLANE, and the color to the VGA_COLOR_PLANE
LED Controller
- The LED controller is a relatively basic one. Simply store to address 0, 1, 2, or 3 on the LED controller to turn on/off a light. It toggles the light settings.

Compiling your code
Using the C Compiler

Useful Files
CSE378 BIOS Source
CSE378 Bootloader Software
Top level board design - Just insert your processor into the design and connect the ports.
Waveform for top-level design - Waveform that uses InfoGen component. (Use with these aliases)
Updated lib378 information - Note that the new components that you need are in the library.
UCF File for Lab2(board.ucf) - Use this as your ucf file during implementation
Test Files
Test Fixture
Source File for Test Fixture

This test fixtures tries to exercise all of the various facets of your processor. Unzip into your src directory and add your processor component to regression.bde. It assumes that your are using conservative forwarding practices.

Serial Test Fixture

This is a test fixture that substitutes the serial component for a serial component with a fake FIFO that simulates the input from the serial port. Plug your processor into this and you will be able to see what effects your programs have on the processor. The file includes a test file that should make the lights blink, and you can write your own test files and point to them by editing the parameters on the test fixture. To write your own test .hex file, get the hex version of your program/data, and generate a text file using the following format:

@00400000 - Translates to 010040000000 and means change the current address being pointed to to 0x00400000
01032010 - Translates to 0001032010 and means store the word 01032010 in the current address being pointed to
To end your program, add the line 0200000000. This will cause the bootloader to jump to 0x00400000 and start execution.

Example program (Do NOT include the parentheses when you write a program, they will not be parsed correctly):

0100400000 (Tells BIOS to start storing data at 0x00400000 - so, these are instructions)
(Your program starts below this note, which will not be in the file)
003c098000
0035290040
00200a0000
00200c000f
003c0b0040
00ad2c0000
00214a0001
00154bfffe
0000000000
00200a0000
00200c0000
003c0b0040
00ad2c0000
00214a0001
00154bfffe
0000000000
0008100002
0000000000
(End of program)
0200000000 (End BIOS mode, jump to program start)

The source for this program is included as blink.s in the test fixture. If you choose to use your own hex file, be sure to modify the parameters for the serial_tf component to know where the new file is located.

To use the test fixture, plug your processor into the top level test fixture design provided with board_tf.bde. Then, stimulate the SYSTEM_CLOCK input with a 100Mhz clock, and use formula stimulators for the reset signals. Set SW0 to the formula "0 0ns, 1 40ns", and SW3 to "0 0ns, 1 160ns". Now, start your simulation like normal and you should be able to boot into the BIOS and load the file into your IRAM for execution.

Due Dates
Progress Reports - Friday, May 5th
Software - Saturday, May 13th
Hardware - Tuesday, May 16th

Turn-in
For the software part of the lab, use ActiveHDL's "Archive Design" command and submit the resulting archive via turnin. Turnin is now available on attu.

Computer Science & Engineering
University of Washington
Box 352350
Seattle, WA 98195-2350
(206) 543-1695 voice, (206) 543-2969 FAX
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