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 CSE 378 Fall 2006
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Programming the Boards - Part 2: Synthesis

Setting up Synplify
Now that you're ready to synthesize your design, you will need to configure some settings for Synplify Pro 8.6 in order to ensure that the process takes place as expected. To begin, go to the Design Flow window and click on the Options button next to the Synthesize button. This will bring up a menu with many options. The important ones are "Top Level Unit", "Family", "Device" and "Speed Grade". Make sure that "Top Level Unit" is set to the top level design in your project, that "Family" reads "Xilinx8x VIRTEX2P", "Device" is set to "2vp30FF896", and "Speed Grade" is set at "-6".

Configuring the Device Family

Next, you will want to add lib378 to synthesis. If lib378 is in the current workspace, right click on its entry in the panel on the right, and select "Add all files to library".

Adding lib378 to the Design for Synthesis

Finally, you will need to add a compiler directive to the setup. Go to the "Generics/Parameters" tab and add "SYNTHESIS" (without the quotes) under Verilog Compiler Directives.

Adding the SYNTHESIS compiler directive

Now that you have set everything up correctly, ensure that all of the files that your design relies on are included in the synthesis. You can add files by right clicking on them and selecting "Include in Synthesis". Once you have completed this step, proceed to the next step to run Synplify by clicking on the Synthesis button next to the Options button.

Running Synplify Once Synplify has started up, click on the Run button to start the synthesis process.

Initial Synplify Screen

Once the synthesis has completed its run, check the warnings produced by looking at the message tab. You may find it useful to consult this list to identify major problems with the design.

Checking the Warnings Encountered during Synthesis

Once you are satistifed with your synthesis, close Synplify and return to Active HDL. Now, click on "Refresh File List" next to the Synthesis button. Click on the "..." button next to the box for Netlist. Select the folder with the name of your design on it, and select the .edf file with your design's name.

Selecting the Netlist

Now, do the same for the Simulation file, but select the .vhm file with your synthesized project's name on it.

Selecting the Simulation File

Once you have finished that, click OK. You are now ready to move on to implementation.

Previous Section: Active HDL Next Section: Implementation

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