Syllabus

Course Goals

This course provides a theoretical background in, and practical experience with, tools and techniques for modeling complex digital systems with the SystemVerilog hardware description language, including converting software algorithms to hardware. Prerequisites: EE 205/215 and EE 271/CSE 369. This is the last undergraduate course for digital design; other related courses of particular interest include:


Topic List

  • EDA tools and SystemVerilog
  • Finite State Machines (Mealy and Moore)
  • Memories: ROM, RAM, register files, FIFO buffers
  • Algorithmic State Machine (ASM) charts plus Datapath (ASMD)
  • Algorithms to hardware/datapath
  • Timing: static timing analysis, clock domain crossing, pipelining
  • Communication
  • Advanced Testing: assertions, classes, randomization

Course Components

The course consists of the following elements:

  • Lectures: There will be ~18 lectures. In-person attendance is highly encouraged, but slide PDFs and recordings will be made available afterward.
  • Homework: There will be 6 homework assignments throughout the quarter to give you additional practice with the course concepts and programming in SystemVerilog and are intended to set you up for success for the labs and quizzes.
  • Labs and Lab Demos: There are 5 labs (either 1 week or 2 week in duration) followed by a 2.5-week final lab/project. These assignments will reinforce the practical aspects of digital design implementation and SystemVerilog coding skills.
    • We will use the remote FPGA lab at .
    • The necessary software can be accessed in the lab space (ECE 365) or installed on your local machine.
  • Quizzes: There will 5 in-class quizzes throughout the quarter – see the for more information. There is no midterm or final exam. These will reinforce the conceptual and theoretical aspects of digital design covered in the course.

Policies

Grading Policies

We will compute your course grade as follows:

  • Homework: 20%
  • Labs: 50%
  • Quizzes: 30%

We will use a straight-scale grading system with approximately linear interpolation. There will be a very limited number of extra credit opportunities, which will be factored directly into your grades (i.e., 1 extra credit point = 1 normal point). The following thresholds are guaranteed – we may lower, but definitely will NOT raise, them.

  • 95% → 4.0, 86.5% → 3.5, 78% → 3.0, 69% → 2.5, 60% → 2.0

Assignment Policies

  • This course is about design, which is inherently a creative endeavor. Therefore, you should expect some vagueness in the lab specs. If a particular detail is missing from the spec, it is left up to you to decide and define how you will go about it. The TAs will be happy to assist you, however, it is expected that YOU are the one who comes up with your approach and final design and that you are able to describe and defend your choices during lab demos.
  • Debugging is often time-consuming and frustrating, but it is one of the most important skills to develop. TAs will provide guidance but will not fully debug your programs.
    • Simulations are an important tool to help you debug your programs, so you should expect to use test benches and ModelSim extensively in this course.
  • Homework may be (optionally) completed in groups of up to 4 students; you may change group members in-between assignments. This is to encourage you to interact with your peers and to help you work through your gaps in understanding and misconceptions.
  • Labs may be (optionally) completed with a partner; you may change partners in-between labs. These are a combination of a lab report and a lab demo, which are graded independently:
    • The lab reports are submitted to and are due Friday @ 11:59 pm, which is before you demo with a TA. This is to encourage you to do all of your testing and data collection as you develop your lab and will prepare you for the lab demo.
    • The lab demos are done synchronously with a TA, typically during your assigned 15-minute lab demo slot on Monday or Tuesday. Lab demos can only be done after submitting the associated lab report.
      • Lab demos are a chance for you to present your work and get feedback as you get more comfortable with SystemVerilog and the DE1-SoC. The TAs will also have 1-2 short questions for you to answer about the lab.
      • It is possible to get a full demo score even if you do not finish the lab! Please come and present what work you did and where/how you got stuck so the TAs can give you feedback and tips for future labs.
      • Missing a lab demo will result in a zero grade for the entire lab; when working in a partnership, both partners must be present in order to demo. We reserve the right to adjust grading based on individual contributions to the partnership.
  • If you plan to work with others this quarter, make sure that you read our thoroughly!

Late Policy

  • Homework and lab reports have lateness counted in days after their 11:59 pm deadlines.
    • Homework may be submitted at most 1 day late. Lab reports may be submitted at most 2 days late.
    • You will be given 6 late day tokens for the quarter that will cancel out penalties for late submissions. Once you have exhausted your late day tokens, each remaining late day will become a 10% penalty assessed on one of your late submissions, though chosen to maximize your overall score.
    • There is no bonus for having leftover late days at the end of the quarter.
  • Lab demos cannot be penalized but must be done within a week of the lab report due date.
    • Unless you are submitting your lab report late, you will be expected to demo during your assigned lab demo slot each week. Drop-in lab demos are not allowed; please contact us ahead of time.

Student Conduct and Academic Integrity

The University of Washington Student Conduct Code (WAC 478-121) defines prohibited academic and behavioral conduct and describes how the University holds students accountable as they pursue their academic goals. Allegations of misconduct by students may be referred to the appropriate campus office for investigation and resolution. More information can be found online at .

We can learn a lot from working with each other and it can make the course more enjoyable, but we also want to ensure that every student can get the maximum benefit from the material this course has to offer. Keep in mind that the overall goal is for *YOU* to learn the material so you will be prepared for job interviews, projects, etc. in the future. Cheating consists of sharing code or solutions to assignments by either copying, retyping, looking at, or supplying a copy of a diagram or file. Examples include:

  • Coaching a friend to arrive at a solution by simply following your instructions (i.e., no thinking involved).
  • Copying code from a similar course at another university or using solutions/code on the web, including GitHub, Chegg, and AI generative tools like ChatGPT.
  • Communicating your solution with another student via electronic or non-electronic means.

Cheating is a very serious offense. If you are caught cheating, you can expect a failing grade on the assignment and the initiation of a cheating case in the University system. If you feel that you are having a problem with the material, or don't have time to finish an assignment, or have any number of other reasons to cheat, then talk with the instructor. Just don't cheat. If you are in doubt about what might constitute cheating, contact the instructor and describe the situation and we will be happy to clarify it for you.


Disability Resources

Your experience in this class is important to us. It is the policy and practice of the University of Washington to create inclusive and accessible learning environments consistent with federal and state law. If you have already established accommodations with , please activate your accommodations via myDRS so we can discuss how they will be implemented in this course.

If you have not yet established services through DRS, but have a temporary health condition or permanent disability that requires accommodations (conditions include but not limited to; mental health, attention-related, learning, vision, hearing, physical or health impacts), contact DRS directly to set up an Access Plan. DRS facilitates the interactive process that establishes reasonable accommodations. Browse to to start the process as soon as possible to avoid delays.

You can refer to the university policies regarding for more information.


Religious Accommodations

Washington state law requires that UW develop a policy for accommodation of student absences or significant hardship due to reasons of faith or conscience, or for organized religious activities. The UW's policy, including more information about how to request an accommodation, is available at . Accommodations must be requested within the first two weeks of this course using the .


Extenuating Circumstances and Inclusiveness

We recognize that our students come from varied backgrounds and can have widely-varying circumstances. If you have any unforeseen or extenuating circumstance that arise during the course, please do not hesitate to contact the instructor in office hours, via email, or private Ed Discussion post to discuss your situation. The sooner we are made aware, the more easily these situations can be resolved. Extenuating circumstances include work-school balance, familial responsibilities, military duties, unexpected travel, or anything else beyond your control that may negatively impact your performance in the class.

Additionally, if at any point you are made to feel uncomfortable, disrespected, or excluded by a staff member or fellow student, please report the incident so that we may address the issue and maintain a supportive and inclusive learning environment. Should you feel uncomfortable bringing up an issue with a staff member directly, you may consider sending or contacting the .