Using a verilog test fixture file for testing a design is a little different then what we have done so far. In comparison with our past test fixtures, a sequential test fixture is slightly more complex. Because a sequential circuit relies on tracking the passage of time, we need to simulate the clock. Since the clock simply goes from high to low and back to high again over and over, we need the equivelent of an endless 'for-loop'. The way we do this is with the 'forever begin' statement. Verilog allows us to have multiple timings at the same time. So we can simulate the clock with a forever begin and then also have the good old 'initial begin' we have been using. The only thing we need to be concerned about when testing our sequential circuit is the relationship between the time the clock changes with respect to when we change the values of the inputs. Because the flip-flops are waiting for the clock edge before sampling their inputs, a changing input at the same instant the clock changes can have undesired results. A good rule of thumb is to change inputs of the test fixture about half-way between the time the clock goes from high to low or from low to hi. Also, don't forget that if there is delay in the circuit design (i.e. schematics with gate delays), you must allow enough time for the circuit to settle after changing inputs before the change in the clock edge. Here is a generic test fixture:

`timescale 1ns/1ns

module counter_mod;

`include "counter.tfi"

initial begin clk = 0;

forever begin 

#5 clk = 1; 

#5 clk = 0; 

end 

end

initial begin

//change inputs down here, allowing time for the circuit to settle

end 

endmodule

Looking at an working example might help.