Synchronous Mealy FSM
module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state variables always @(posedge clk) if (reset) state = `zero; else case (state) `zero: // last input was a zero begin out = 0; if (in) state = `one; else state = `zero; end `one: // we've seen one 1 if (in) begin state = `one; out = 1; end else begin state = `zero; out = 0; end endcase endmodule