PPT Slide

5 – Sequential Logic

© 1996 Gaetano Borriello

Metastability and asynchronous inputs: terms and definitions

• Clocked synchronous circuits

  • inputs, state, and outputs sampled or changed in relation to acommon reference signal (called the clock)
  • e.g., master/slave, edge-triggered

• Asynchronous circuits

  • inputs, state, and outputs sampled or changed independently of acommon reference signal (glitches/hazards a major concern)
  • e.g., R-S latch

• Asynchronous inputs to synchronous circuits

  • inputs can change at any time, will not meet setup/hold times
  • dangerous, synchronous inputs are greatly preferred
  • cannot be avoided (e.g., reset signal, memory wait, user input)

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