PPT Slide
Comparison of latches and flip-flops
Type When inputs are sampled When output is valid
unclocked always propagation delay from input change latch
level-sensitive clock high propagation delay from input change latch (Tsu/Th around falling or clock edge (whichever is later) edge of clock)
master-slave clock high propagation delay from falling edge flip-flop (Tsu/Th around falling of clock edge of clock)
negative clock hi-to-lo transition propagation delay from falling edge edge-triggered (Tsu/Th around falling of clock flip-flop edge of clock)