PPT Slide
Rules for interconnecting components and clocks
- guarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory elements
- we'll focus on systems with edge-triggered flip-flops
- found in programmable logic devices
- many custom integrated circuits focus on level-sensitive latches
Basic rules for correct timing:
- (1) correct inputs, with respect to time, are provided to the flip-flops
- (2) no flip-flop changes state more than once per clocking event