PPT Slide
3 – Combinational Logic Implementation
Hazards/glitches: unwanted switching at the outputs
- occur when different paths through circuit have different propagation delays
- as in pulse shaping circuits we just analyzed
- dangerous if logic makes a decision or causes an action while output is unstable
- may need to guarantee absence of glitches
Usual solutions
- 1) wait until signals are stable (by using a clock) preferable (easiest to design when there is a clock – synchronous design)
- 2) design hazard-free circuits sometimes necessary (clock not used – asynchronous design)