Flip-flop summary (con’t)
Clear and preset inputs are highly desirable in flip-flops
- Used to reset logic to a known state
Clear or Reset the state to a logic 0
- Synchronous: Q=0 when next clock edge arrives
- Asynchronous: Q=0 when reset is asserted
- doesn't wait for clock—quick but dangerous (remember hazards)
Preset or Set the state to logic 1
- Synchronous: Q=1 when next clock edge arrives
- Asynchronous: Q=1 when reset is asserted
- doesn't wait for clock—quick but dangerous