Clock skew
Abstraction: All flip-flops are clocked at the same time
- Difficult to achieve in high-speed systems
- Clock delays (wire, buffers) are comparable to logic delays
- Problem is called clock skew
Original state: IN = 0, Q0 = 1, Q1 = 1
Next state: Q0 = 0, Q1 = 0 (rather than Q0 = 0, Q1 = 1)