CSE370 Assignment 4
Distributed: 21 October
Due: 28 October
Reading:
Chapter 3 (pp. 137-147) and Chapter 4 (pp. 181-194 and 202-224)
of the Katz text.
Tutorial 1: An Introduction to Synario (supplied by
DataI/O Corporation).
Tutorial 2: Top Down Design Using ABEL-HDL and Schematics
(supplied by DataI/O Corporation).
Exercises:
- Complete the CSE370 Synario Tutorial (not the one from DataI/O
handed out in class).
There is nothing to turn in for this exercise.
- Create a Synario project for a full-adder with inputs A, B,
Cin and outputs S and Cout.
Use only NAND gates.
Turn in your schematic.
- Use Synario to simulate your full-adder design for all input
combinations. Please make sure to note any hazards you may detect
in the simulator output waveforms.
Turn in the waveform output of the simulator showing all output
signals.
- Create a Synario project for a 4-bit adder using your full-adder
block as a new symbol.
The inputs of the 4-bit adder should be A3, A2, A1, A0, B3, B2,
B1, B0, Cin and the outputs should be S3, S2, S1, S0, Cout. Your
schematic should not require any other symbols besides your full-adder
symbol.
Turn in your schematic.
- Use Synario to simulate your 4-bit adder design for 7 + 1,
5 + 10, and 6 + 10.
Turn in the waveform output of the simulator showing all output
signals.
Rationale:
- To begin the process of learning how to use modern digital design
tools including gate-level schematic capture with hierarchy.
- To gain facility with gate-level simulation concepts including delay.
- To design and validate a simple combinational logic circuit.
Comments to: cse370-webmaster@cs.washington.edu (Last Update:
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