For the remainder of the course, we will be using a set of tools for entering design specification and then compiling them onto programmable logic. This suite of tools is called Synario and is kindly provided to the department through a donation from DataI/O Corporation of Redmond, WA. You should think of Synario as an environment under which a multitude of tools are run. Some of these tools (e.g., schematics editor, simulator, etc.) are from DataI/O and some are not. Besides tying all these tools together into a coherent design environment, Synario also provides us with tools to manage our design information.
The design tools for this course all run on Windows'95/NT PCs. If you are not familiar with this environment, then please seek the help of others in the class who are and work with them on the tutorial portions of this assignment (exercise 1). If you are already familiar with the PC environment, then please lend a hand to your fellow students who are not.
You will be using the Synario tool suite for the remainder of
your assignments in CSE370 and then, possibly, again (at a more
advanced level) in CSE467. Synario can be found on all the PCs
in the laboratory in 232 Sieg. You will find Synario 2.3 in the
Hardware Design Lab group in the Program Manager. Open that icon
and you should see the following (or something quite similar):
The important icons in this window are Synario and StateCAD 3.00.
We will be using StateCAD a bit later on in the quarter. For now,
focus your attention on Synario. Double-click on the Synario icon
and the Synario Project Navigator window should pop on the screen.
A Synario project is the entire collection of files needed for
a design. These include schematic drawings, specifications in
a hardware description language, specifications of the input stimuli
needed for simulation, and the devices to be used in realizing
the design (e.g., programmable logic devices). To begin our tutorial
design, lets create a new project by selecting the "New Project
..." entry in the "File" menu. You should create
all your files in your own personal directories (which you should
be able to locate on the X or Z drives as X:\username, for example).
In the following examples, I use the cse370 course directory on
the U drive. Give your project a simple name. I chose to use "simple".
The important characteristics of the name are that it be no more
than 8 characters long (for DOS compatibility reasons) and that
it not conflict with basic names of devices which may already
be defined with the tools (e.g., AND or NOT, etc.). The window
below is used to create a new project. You may want to already
create a sub-directory for it within your main directory as Synario
will generate a whole bunch of intermediate files (which you do
not want to look at or play with as the they are not all ASCII
and you may create an inconsistent state for the tools if you
edit or delete them) and its probably good policy to keep these
neatly collected in one subdirectory. I created the subdirectory
within the cse370 directory using the file manager.
After you press "OK", the Project Navigator will show
the following:
Synario has created an Untitled project with a virtual device to be used for its implementation. We will use this virtual device for all this tutorial (and all the exercises in this assignment). Later on in the quarter we'll learn how to select specific devices to be used to realize the design and how to tell Synario which parts of the design are to realized by which device.
The next step is to create a design specification. For now, to
enter the gates that make up our design, we are going to use a
schematic drawing. You can create a new source file by selecting
the "New ..." entry in the "Source" menu.
This will provide you with a choice of the type of specification
you want to enter. Choose "Schematic" as shown below.
In this case I used the same root name for the schematic as for
the project. However, this is not required as you may have multiple
schematic drawings for one project.
In this case I used the same root name for the schematic as for
the project. However, this is not required as you may have multiple
schematic drawings for one project. Once you enter this name and
click on "OK", a schematic diagram editor window will
pop-up on the screen. This is the first of the tools of the Synario
tool suite that we will be using.
The Schematic Editor allows us to draw gate level schematics by
selecting gates and placing them on the document and then connecting
them. For this tutorial, we are going to make a schematic diagram
that is only a single AND gate. To draw an AND gate on the drawing,
select the "Symbol ..." submenu of the "Add"
menu of the Schematic Editor and the following palette for the
symbol library should appear.
The symbol library is provided by Synario to facilitate starting a schematic diagram. Later on we'll see how to define our own symbols so that our schematics can include hierarchy (elements composed of simpler elements). Select the "GENERIC\GATES.LIB" sub-library. You'll notice that many primitive gates are provided including: AND, OR, NAND, NOR, and NOT. There are versions of the gates with different numbers of inputs (up to 4) and with some of the inputs inverted (bubbles on the inputs). For example, G_2AND is a 2-input AND gate while G_3NAND2 is a 3-input NAND gate with 2 inverted inputs. Select a G_2AND gate and place it in your schematic drawing. Notice that the cursor turns into the gate when you place it over the Schematic Editor window.
Your schematic drawing should now look like this:
Experiment with moving/dragging the symbol around on the drawing by using the items in the "Edit" menu. Try deleting and re-placing another instance of it (by re-selecting it from the library as above). Try zooming in and out on the drawing by using the items in the "View" menu. Lets add some wires to the drawing by using the "Wire" command in the "Add" menu. Wires will be used to connect the inputs and outputs of our AND gate to other elements of our schematic. For now, just add a short wire to each input and output.
The next step is to add some names to these wires and thus to
the inputs and outputs of our AND gate. We can do this by using
the "Net Name" command of the "Add" menu.
You note that the schematic editor prompts you for a name at the
bottom of its window. Enter a name, say "a", and hit
return. The cursor will turn into an "a" and you can
click on the end of the wire to which you want to end the name.
Notice how the name is automatically adjusted to line up with
the end of the wire. Repeat this for the other input and the output
of the AND gate so that your schematic now looks like this:
The last step is making our schematic drawing is to add I/O markers
that indicate which signals we expect to be the primary inputs
and outputs of our entire design. In this case, we'll be interested
in all three of them. However, in larger designs, there may be
many internal signals that won't be observable at the pins of
the devices we'll use to realize our design. To add I/O markers
select "I/O Marker" in the "Add" menu. Select
"input" for the type and click on the ends of the inputs
wires "a" and "b". You'll notice that a small
arrow shaped box is placed at the end of the wire (pointing in
to indicate input). Now do the same for our output to obtain a
schematic like the following:
Now save and close the schematic editor window. The project navigator
window will now show that a schematic drawing has been entered
for this project and it is called "simple" and is stored
in the file "simple.sch" which appears in parentheses.
If you select the schematic drawing in the "Sources in Project"
sub-window of the project navigator window, you'll notice that
a set of things will appear on the right sub-window labeled "Processes
for Current Source". These are all the things that Synario
can think of to do with our schematic drawing.
We may want to navigate its hierarchy, compile it into logic equations,
minimize that logic, and/or look at the reduced equations derived
from this process. The nice thing about Synario is that it worries
about the dependencies between these tools and which files are
the inputs to one and the outputs of another. We can simply select
the thing we are interested in doing and Synario does it. For
example, if we want to see the reduced equations, we can just
double-click on that entry in the "Processes" sub-window
and whole bunch of activities are started off.
The check marks mean that the process completed successfully.
If it had not, we would see either a yellow exclamation point
indicating that warnings have been generated or a red "x"
indicating that a fatal error had occurred and that the processes
could not continue. We can view the results of the operations,
that is, the reduced equations, by clicking on the "View"
button at the bottom of the "Processes" sub-window.
Errors and warnings can be viewed by using the "Log..."
button. In this case, the reduced equations file looks like this:
Synario 2.30 Design and created Fri Oct 18 17:24:42 1996 Title: simple.bls P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- 1/2 2 1 Pin c ========= 1/2 Best P-Term Total: 1 Total Pins: 3 Total Nodes: 0 Average P-Term/Output: 1 Equations: c = (b & a); Reverse-Polarity Equations: !c = (!b # !a);
Note that it includes a list of the gates, their fan-in and fan-out values, and the equations for each gate (remember that these can be much more complex than the simple AND gate we are using) as well as the complement function.
Now that we have our schematic entered and verified that the compilation/optimization
process has produced reasonable results, it is time to validate
our design by simulating it. To do this we need to create the
simulator input which consists of a translation of the equations
into something the simulator understands and a specification of
the input signal values to apply to the circuit. To do this, lets
start by adding a new "Source" to our design. This time
select "Verilog Text Fixture" as the new source document.
You will be prompted to associate this test fixture with one of
the existing design elements. In our case, since the AND gate
is our entire device, we'll associate it with the "Virtual
Device", namely, our entire design. In larger designs, we
may conduct simulations of pieces of the design and will then
have different test sources associated with various parts.
We'll call our test fixture "simple.tf".
Notice now that the new file has been added to the "Sources"
sub-window. If we select it, we'll note there are two items in
the "Processes" sub-window associated with it. These
are two simulators. We will be using the "Verilog" simulator.
Note that sub-programs of Synario are shown as they would be by
Windows, as boxes with a menu bar.
Some other things have changed as well. If we now re-select the
schematic "Source" we'll see that there are two new
"Processes" associated with it. This has happened because
Synario has figured out that we are not interested in simulating
our design and the items listed correspond to the preparation
of files for input to the simulator. In this case, these are a
functional simulation model of the guts of the AND gate and a
test "fixture" to be used to connect to the input stimulus
file we will soon prepare.
The input stimulus file must be written in the Verilog language.
Verilog is a hardware description language with syntax very similar
to C. We will only be using Verilog for driving our simulator,
that is, telling it what input signal we want when during our
simulation. If you continue on to CSE467 or CSE471 you'll learn
a lot more Verilog. For our purposes, a very small subset is required.
We will edit the "Source" file "simple.tf"
by selecting it and using the "Open..." button at the
bottom of the "Sources" sub-window. This will cause
a simple text editor to pop-up. The text we will enter will be
like the following:
For our purposes, most of this is boiler-plate. The timescale will always be set to the same values. We need to give the module a name (different from the name of our schematic - this is important) and tell the simulator to use the models that Synario will help us create (the `include "simple.tfi" statement). Finally, there is an "initial" block that specifies the values of the inputs and how much time to let pass. The "#" symbol is used to denote the passage to some units of time. In this case, we begin at time 0 with a and b both set to 0, then we allow five time units to pass (to let the inputs propagate through the gate and reach stability - note that in this simulator each basic gate has a unit delay, that is, one time unit - so that 5 is more than enough in this case) and set b to 1, another 5 time units later we set a to 1 as well, and finally after yet another 5 time units we set b back to 0.
We now save this file and can exit from the text editor. We start
the simulation by selecting the test fixture in the "Sources"
sub-window and double-clicking on the "Verilog Functional
Simulation" in the "Processes" sub-window. This
will eventually (there is a lot going on here for this simple
AND gate - be patient) bring up the simulator window. As you can
see its set up to start running a simulation from time 0 and up
to 1000 with a step interval of 1000.
We can also open a waveform viewer to see the progress of the
simulation and the values on the signals as a function of time.
To do this, select "Waveform Viewer" in the "Window"
menu of the simulator. You will then see another window that looks
like this:
Unfortunately, there are no signal names displayed in this waveform
viewer. That is because a typical design will have many more signals
than could possibly be displayed in a waveform viewer the size
of a PC screen. Therefore, you are expected to specify which signals
you are interested in observing. To do this, click on the "Debug"
button of the simulator. You will see the following:
To make signals visible on the waveform viewer, select them in
the "Available Signals" list and then click on the "Monitor"
button. On the right, you'll see those signals listed with their
initial value. Before the simulation starts, this initial value
is unknown and is depicted as an "X". At this point,
you should also see the signal names on the right hand side of
the waveform viewer (to the left of the 0 point on the time axis).
We can also change the duration of the simulation to 25ns and
make the step size be 5ns. If we now click on the step button,
the simulation will advance 5ns (the step size).
The waveform editor will be automatically updated with the values
of the signals in the interval (0, 5ns). Note that the output
c remains undefined for 1 time unit. That is the time it takes
for the input signals to affect the value of the output under
a unit delay model. Therefore, by t=1ns the value of the output
is already stable and defined. We could have changed the inputs
again at t=2ns, but we had decided to wait until t=5ns.
If we now click on the "Step" button another 4 times,
we'll reach t=25ns and the waveform viewer will show the following
waveforms. Note that our AND gates functions as expected. We have
applied all possible input combinations to our gate (allowing
the output ample time to settle in between input changes).
It is an excellent idea to save work periodically. I recommend it highly. Save the project by selecting "Save" in the "File" menu of the project navigator.
We will now turn our "simple" design into a block to
be used in future designs. In this case, of course, this is sort
of silly as it only contains an AND gate. However, we could have
had an arbitrarily large schematic and would now encapsulate it
all in a symbol we can use in other schematics. This is how we
can build up hierarchical schematic diagrams using Synario. To
create a new symbol, we need to go back into the schematics editor.
There are many ways to do this. A simple way is to just double-click
on the "simple" schematic "Source" in the
project navigator. Once the schematic editor window is open, we
can select "New Block Symbol" from the "Add"
menu of the schematic editor. The following dialog box pops-up.
For now, we can simply press the "Use Data From This Block"
button since we want to create a new symbol with the same inputs
and outputs as the schematic diagram with our AND gate. This yields
the following:
Once we create our new symbol it will be added to a local library
that we can now see in the "Symbol Libraries" palette
that we can cause to pop-up through the "Symbol" entry
in the "Add" menu.
We can now close this schematic. When we are ready to use our
new symbol in a new schematic, we can get to it in this manner.
It will appear in the schematic as the following:
The symbol will be stored in the same directory as the schematic from which it was defined. That means we should use the same directory for any designs that will require this symbol. Later on, we'll learn how to make the symbol accessible by any design.
That is the end of this simple tutorial. You should also read
through the DataI/O tutorials for further information and learn
to use the Synario manuals that are available.