CSE370 Assignment 8
Due: 12 March 2010
- Unfortunately, there are no chapters in the CLD2e on
- The MIPS2000 processor is a simplified version of the
one described in Patterson & Hennessy's Computer Organization and
Design, Morgan-Kaufmann. There should be plenty around the
department as this is the CSE378 textbook.
- You'll find the files you need to create your own
Active-HDL project for our version of the MIPS
R2000 in this zip file. Download this file, extract the pieces, and
open the file mips2000.aws into a new Active-HDL workspace. This
contains the complete Verilog files you'll need for the detailed
operation of the processor's data-path.
The Verilog for the controller is incomplete.
- Using the lecture
slides on computer organization as a guide, determine the
register-transfer operations and their corresponding control signals that
will implement all 11 instructions on slide 20. The controller’s Verilog description already has some states filled in
(see controller.v). Please follow the style and pattern that
was reviewed in class. All
instructions will start with an instruction fetch cycle, followed by an
instruction decode cycle, and these optionally followed by one or more
cycles to execute the specifics of the instruction. Each state
should be done in the style of slides 32, 35, and 38 with the direction of
data-flow and values of control signals clearly labeled. You don't
need to redo the instruction fetch and decode cycles as these are
identical for all 11 instructions. However, you do need to turn in
the instruction execute cycles for each of the 11 instructions (states EXE
1, EXE 2, and EXE 3 on slide 55). Use this figure
as a template for EACH of these states and a table like the one on slide 54 to list your states (columns) and
control signals for each state.
Turn in eight of these tables for each of the 11 instructions (you
can combine the first four – ADD, SUB, OR, AND – into one). This is the same information as on
slides 33, 36, and 39 for the ADD instruction.
- The memory is already configured to initialize with a
program to compute the Nth Fibonacci number (see memory.v).
The value of N is stored in location 254 in the memory and the answer will
be deposited in location 255 (you'll want to make sure that this memory
location is observable on your simulation waveforms). This program is your test fixture.
- Turn in your own simulation waveforms for your
processor executing this entire program (from reset at the start to
executing the halt instruction and reaching the "halt" state) as
well as your Verilog file for the controller
(the completed controller.v). This
should be well-commented and accompanied by a state diagram (completed
slide 55). At the very minimum, the following signals should be
displayed on your waveforms: clock, reset, memory address bus, memory data
bus, memory read, memory write, program counter contents, instruction
register contents, ALU output, contents of memory location 255, and the
state register of your controller. Make sure they are in this specific
order at the top of the waveforms. You should feel free to include
any other signals you wish – for example, controller state.
- On your waveforms, clearly label when your processor
first computes the 1st, 2nd, 3rd, 4th, 5th, and 6th Fibonacci numbers.
They should be visible on the ALU output. Also, indicate when the
clock cycle in which the processor fetches each instruction and when it
reaches the "halt" state.
- To develop and understanding of the operation of a
- To gain facility with the specification of
register-transfers for such processors.
- To complete the controller specification for a simple
processor and simulate it running a small program.
Comments to: email@example.com