a) Design and test a 1-bit adder that has 3 inputs, A, B, Cin and three outputs: Sum, P, and G. P and G are the propogate and generate functions accordingly, and are defined in the following way: G = AB, P = A xor B. You may do this either with Verilog or a schematic
b) Using your 1-bit adder, design and test a 4-bit adder component which has three input busses, A[3:0], B[3:0], Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0]. (This 4-bit adder is just four independent copies of the 1-bit adder.) You must use a schematic for this.
c) Design and test a 4-bit carry-lookahead component that has three inputs, P[3:0], G[3:0], Cin, and three outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the block propagate and block generate functions. You must use a schematic for this.
d) Using your 4-bit adder component and 4-bit carry-lookahead component, design and test a 16-bit carry-lookahead adder. You must use a schematic for this.
e) What is the size (# of gates) and delay of your 16-bit carry-lookahead adder?
f) If you continued and made a 64-bit carry-lookahead adder using these components, what would be the size and delay of that circuit?
Turn-in your implementations/console outputs for part c,d and the answers to part e,f.