7.22.
7.25.
7.29.
Translate the two following state machine into Verilog modules (one per module). Use the Catalyst Collect It tool to submit your Verilog code. Please put both modules in a single file (but put the two state machines in different modules!). Remember to check your submission!!!
This Verilog file may be useful as a starting point for testing your code. You should be able to simulate it with your code to see if the expected outputs are printed.
- This state machine has a 1-bit input and a 2-bit output. Each state is
labeled with its output.
- This state machine has a 2-bit input and a 1-bit output. Assume that if
there is no transition out of a state for a particular input pattern,
there is an implicit transition from that state back to itself with the
output 0.
