Homework 7

Distributed Thursday, November 8, 2007
Due before 10:30, Wednesday, November 14, 2007

Please put your full name and lab section letter on your homework.

Always remember to staple your work, if it is multiple pieces of paper.

If you choose, indicate on the top of your assignment roughly how much time you spent on it. This information will have no impact on your grade; it will only be used by an inexperienced course staff to gauge the volume of work to assign.

  1. (15 points)
  2. (25 points)
  3. (25 points)
  4. (25 points)
    Translate the two following state machine into Verilog modules (one per module). Use the Catalyst Collect It tool to submit your Verilog code. Please put both modules in a single file (but put the two state machines in different modules!). Remember to check your submission!!!

    This Verilog file may be useful as a starting point for testing your code. You should be able to simulate it with your code to see if the expected outputs are printed.

    1. This state machine has a 1-bit input and a 2-bit output. Each state is labeled with its output.

    2. This state machine has a 2-bit input and a 1-bit output. Assume that if there is no transition out of a state for a particular input pattern, there is an implicit transition from that state back to itself with the output 0.