Due: 22 October 2004

This homework assignment will be concerned partly with using Active-HDL, although you will be practicing concepts you have used from class.

The Intro to Active-HDL Tutorial #2 continues from Tutorial #1 and covers hierarchy, signal busses and test fixtures. The Tutorial is closely related to problem 2 of this homework. It would be a good idea to read over problem 2 before you do the tutorial.

Work through this tutorial, making sure you understand everything that it covers. Again, if you run into problems, send us email or try to find us. If you have comments on how to make the Tutorial better, please send me email.

A1. This problem involves the following function of three inputs, A, B and S: If S=0, then the output=A; if S=1, then the output=B. (This is sometimes known as an if-then-else gate.)

a) Find both the minimal SOP and POS circuit implementation of this function.

b) Using Active-HDL, enter the schematics for both these circuits in the same block diagram. Use the test fixture in the following file to test your circuits: if_then_else_tf.v Print the waveform from your simulation. Are there glitches in the output of your circuits? Explain what causes them, and explain why the circuits have *different *behaviors.

c) In a new block diagram, design a single circuit implementation that does not have glitches on the output. Use the same test fixture, and print the waveform from your simulation.

A2. Design a full-adder component with inputs A, B and Cin, and outputs S and Cout.

a) Find the minimal 2-level circuit implementation for S and Cout. Make a component for this comparator using Active-HDL. Use the text fixture fulladder_tf.v to test your component. Print your schematic and console output from the simulation.

b) Now design a 4-bit ripple-carry adder using four of your full-adders. Use the test fixture adder4_tf.v to test your component. Print your schematic and console output from the simulation.

c) Now design an 8-bit ripple-carry adder using two of your 4-bit full-adders. Use the test fixture adder8_tf.v to test your component. Print your schematic and console output from the simulation.

d) What is the worst-case delay of your 8-bit adder? (Don't look at the simulator waveforms! Why not?) What would be the size and delay of a 512-bit ripple-carry adder?

e) Now design an 8-bit carry-select adder. A carry-select adder does not wait for the low-order 4 bits to finish before starting on the high-order 4 bits. Instead, it adds the high-order 4 bits with **two** 4-bit adders: one uses 0 for the carry in while the other uses 1. When the carry out from the low-order 4 bits is available, it selects the appropriate high-order results and throws away the other. Use the test fixture adder8_CS_tf.v to test your component. Print your schematic and console output from the simulation.

f) What is the worse-case delay of this 8-bit carry-select adder? Can you suggest how to make larger carry-select adders to achieve the smallest delay?

- CLD-II, Chapter 3, problem 3.1, parts c, and d.
- CLD-II, Chapter 3, problem 3.8, parts a, b, and d.
- CLD-II, Chapter 3, problem 3.11, part a.
- CLD-II, Chapter 3, problem 3.26, all parts.

- To practice and gain facility with two-level canonical forms.
- To practice basic combinational logic design.

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