//--------------------------------------------------------------------------------------------------
//
// Title       : fulladder_tf
// Design      : HW3
// Author      : Lucas Kreger-Stickles
// Company     : uw
//
//-------------------------------------------------------------------------------------------------
//
// File        : fulladder_tf.v
// Generated   : Thu Apr 15 14:34:22 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : Run this test fixture for 90 ns to test your full_adder circuit
//
//-------------------------------------------------------------------------------------------------
`timescale 1ns / 1ns

module fulladder_tf ( A ,Cin ,B ,Cout ,S );
input Cout ;
input S ;
output A ;
output B ;
output Cin ;
reg A ;
reg B ;
reg Cin ;

integer i;
  
initial begin 
  for (i=0; i<8; i=i+1) begin
    {A,B,Cin} = i;
    #10;	  			  
	if ({Cout,S} != A+B+Cin) begin
		$display("Error: on A: %d, B: %d, Cin: %d",A,B,Cin);
		$stop;
	end		  
  else begin   
	  	 //$display("Correct: on  A:%d, B:%d, Cin:%d ",A,B,Cin);
	  end//else
  end // for (i=0; i<8; i=i+1)  
  $display("Test Passed: No errors found");

end // initial begin

endmodule