Course Schedule (Subscribe)
DATE
TOPIC
QUIZ
LABS
Week 1
Fri, Oct 02
SEC 00 Info Session, Q&A (Optional)
Week 2
Tue, Oct 06
LEC 01 Combinational Logic
Reading: B&V: § 1.0-1.4, 2.0-2.7
Wed, Oct 07
DEMO 01 Lab Kit Pickup
Week 3
Tue, Oct 13
LEC 02 More CL, Verilog Basics
Reading: B&V: § 2.9-2.10
Fri, Oct 16
SEC 02 Combinational Logic and Modules
Week 4
Tue, Oct 20
LEC 03 Karnaugh Maps
Reading: B&V: § 2.11-2.12, 2.14
Fri, Oct 23
SEC 03 Test Benches
Week 5
Tue, Oct 27
LEC 04 Arithmetic, Sequential Logic
Reading: B&V: § 3.0-3.3.3, 3.3.5, 5.4-5.4.3
Fri, Oct 30
SEC 04 Sequential Logic
Week 6
Fri, Nov 06
SEC 05 Finite State Machines
Week 7
Tue, Nov 10
LEC 06 Timing Constraints
Reading: B&V: § 5.4.4, 5.15
Fri, Nov 13
SEC 06 User Input and Top-Level Modules
Week 8
Tue, Nov 17
LEC 07 Encoders, Decoders, Registers, Counters
Reading: B&V: § 4.0-4.1.1, 4.2-4.3
Fri, Nov 20
SEC 07 Common Issues When Connecting Modules
Week 9
Fri, Nov 27
SEC 08 Problem Decomposition
Week 10
Tue, Dec 01
LEC 09 TTL, Computer Components, FPGAs
Reading: B&V: § B.6