CSE369: INTRO DIG DESIGN

Welcome. Please visit here for basic course information and links to the webs for earlier quarters.

Announcement

Lectures will be provided as videos linked from this website. There are no classroom lectures but the scheduled time slot (Tue 11:30-12:20) will occasionally be used for quizzes/exams.

Instructors

Georg Seelig (gseelig@uw.edu)
Bin Yu (by23@uw.edu)
Yashin Chen (yashinc@uw.edu)

Grading

70% of you grade will be based on the labs, 30% on exams/quizzes.

Video recordings

Will be posted here. Some of the material covered in the videos (Boolean minimzation, state machines, number systems,...) will be familiar to you from 311. Still, even if you know the material, it might be helpful to take a look a the videos or the notes posted below since some of the emphasis and notations will be quite different from 311.

Lecture Notes

Slides used for the videos. The slides linked here are only partially filled in, other parts are completed in the video lectures. You can use these slides to practice for yourself as you are following the videos. The current version of the slides is from the previous quarter and a few minor changes will still be made to exactly match the videos.

Part01: Intro combinational circuits
Part02: Verilog for combinational circuits
Part03: kmaps
Part04: Sequential circuits and flipflops
Part05: Flipflop realities
Part06: Finite state machines
Part07: Numbers and adders
Part08: Multiplexers
Part09: Registers and counters
Part10: FPGAs

These are the annoted lecture notes from the last quarter. The information is the same as that in the videos.:

Week 1 notes (Intro combinational circuits)
Week 2 notes (Combinational circuits and verilog)
Week 3 notes (kmaps)
Week 4 notes (Sequential circuits and flip flops)
Week 5 notes (Flip flop realities)
Week 5 notes (FSMs)
Week 6/7 notes (Numbers and Adders)
Week 7 notes (Encoders, Decoders, Multiplexers)
Week 8 notes (Registers, Counters, RAMs)

Labs

Lab boards have been donated by Altera, Inc.

Lab assignments for the quarter will be posted here, along with their due dates. Labs 1-7 will be due during the week specified, during your demo slot (demo slot signup sheet will be posted soon). You should actually do the lab during the previous week. Lab #8 is due by 5pm on the date specified.

Lab 1 Lab due April 6/7
Lab 2 Lab due April 13/14
Lab 3 Lab due April 20/21
Lab 4 Lab due April 27/28
Lab 5 Lab due May 4/5
Lab 6 Lab due May 11/12
Lab 7 Lab due May 18/19
Lab 8 Lab due June 1/2

The Quartus II tutorial, for labs #1 and #2, is here.

The Lab #1 files for Quartus are here.

Most of your labs will involve Verilog. The class Verilog tutorial is here. There is also a Verilog Quick Reference Card that may be of interest.

A overview on how to use 4x4 or 8x8 LED arrays is here for some projects in lab #8.

Labs on student machines

If you want to use your own machine to do your labs, then grab the Quartus 14.0 files here.

If you are using a laptop, you can bring it to the lab for demos. If you are using your own desktop machine, or don't want to haul your laptop to lab, you can FTP your files to the lab machines. You may want to use Dropbox, Google Docs, or some other cloud storage account as an intermediate - upload the files from your machine to your Dropbox (for instance) account, then download the files to the lab PCs. It is easiest to just send the entire contents of your lab file, since you'll want the design files, schematics, project, etc. IF YOU ARE DOING THIS, TEST IT BEFORE YOUR DEMO TIME.