Note: this schedule is subject to change. Please check back frequently.
| Lecture |
Date |
Topics |
Textbook Reading |
Paper Assignment |
Slides |
Homework |
|
Jan 6 |
no class |
|
|
|
|
| 1 |
Jan 13 |
Introduction and Metrics |
1.1—1.8 |
none |
overview,
intro,
metrics
|
|
| 2 |
Jan 20 |
Instruction Set Architectures |
Appendix B
Appendix J.2 (RISC ISAs)
Appendix J.3 (x86) |
Colwell et al. - Instruction Sets and Beyond
Optional: Wulf - Compilers and Computer Architecture
|
ISA
|
Critique 1: Colwell essay.
Due: 1/31
|
| 3 |
Jan 27 |
Pipelining Review and Branch Prediction |
skim Appendix A
2.1—2.9 |
Evers et al. - An Analysis of Correlation and Predictability
|
ISA wrapup,
pipelining,
branch prediction
|
Homework 1: Mystery Branch Predictor.
Due: 2/11
Critique 2: Evers branch prediction paper.
Due: 2/7
|
| 4 |
Feb 3 |
ILP part 2 |
|
Kessler - The Alpha 21264 Microprocessor
Optional: Smith & Sohi - The Microarchitecture of Superscalar Processors
|
superscalar,
scheduling
|
|
| 5 |
Feb 10 |
ILP part 3 (Dynamic Scheduling), Simultaneous Multithreading, Data Level Parallelism |
Chapter 3 |
Tullsen et al. - Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
|
scheduling,
multithreading,
DLP
|
Homework 2: Dynamic Instruction Scheduling.
Due: 2/20
Critique 3: Tullsen SMT paper.
Due: 2/22
|
| 6 |
Feb 17 |
Memory Hierarchy |
Appendix C
Chapter 5 |
Jouppi - Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
|
memory hierarchy
|
Homework 3: Mystery Cache.
Due: 2/27
|
| 7 |
Feb 24 |
Multiprocessors |
Chapter 4 |
Lamport - How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
Optional: Adve & Gharachorloo - Shared Memory Consistency Models: A Tutorial
|
virtual memory,
multiprocessing intro,
cache coherence
|
|
| 8 |
Mar 3 |
Multiprocessors part 2 |
|
Gharachorloo et al. - Two Techniques to Enhance the Performance of Memory Consistency Models
|
consistency &
synchronization I
|
Homework 4: Multiprocessors.
Due: 3/14
|
| 9 |
Mar 10 |
Binary Translation, Virtualization, What's Next? |
|
Optional: Dehnert et al. - The Transmeta Code Morphing Software
|
consistency &
synchronization II, virtualization
|
|
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