Homework Set 8   revised Monday, June 2
DUE: Due start of class, Friday, June 6       
 
Collaboration Policy: See homework 1.

Late Homework Policy: See homework 1.

Please show all of your work.Your solutions must be legible…we will not spend time trying to decipher poorly written assignments.

Produce a completed ant-brain design (Lecture 23), with documentation, including the following additions.

1) Crumbs in cell
     Ant eats crumbs in every cell it visits. The maze map is the crumb map. It's 128x128x8 bits, as shown in the lecture slides. The MSB is '0' in all cells, and you should write the 8 bits you read (eating crumbs) back to the memory location with the MSB set to '1' (leaving a crumb).

      2)  You need to design a memory controller in the form of  a state machine to talk to the SRAM.

      3)  You need to deal with startup, exit states.

Hand in:

    Schematics, with top-level block diagram
any Verilog you write
documentation of SRAM memory controller state-machine design

Label all pages with your name and section number, please....