Cached DRAM and IRAM (PIM)
Put some SRAM on DRAM chip
- More flexibility in buffer size than page mode
- Can precharge DRAM while accessing SRAM
- But fabrication is different
Go one step further (1 billion transistors/chip)
- Put “simple” processor and SRAM and DRAM on chip
- Great bandwidth for processor-memory interface
- Cache with very large block size
- Can’t have too complex of a processor
- Need to invest in new fabs
- Already done in a small way for graphics