CSE P 548: Computer Architecture - Spring 2005

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Sim3mp Sim3mp is a reimplementation of SimpleScalar using C++, written by Mark Oskin. The level of detail of sim3mp is around that of simcache but it models a three state bus-based cache coherency multiprocessor system, although it does not simulate an actual out-of-order pipeline and there is no virtual memory. There are L1 instruction and data caches per processor and a unified L2 cache. The L1 caches do not have to snoop because the L2 caches do snoop i.e. if a processor is writing to a line in its L1 data cache, then the corresponding line in the L2 cache will be in the exclusive state. Naturally this means that the caches must have the inclusion property and the L1 caches must be write-through because they do not store coherency state. It may prove necessary to modify the L1 caches to store coherency state when changing the existing three state protocol into a four state protocol. This is how to build sim3mp: Expand the .tar.gz file. You may need to rename the file from .tar.tar to .tar.gz Ensure that you have /cse/courses/csep548/05sp/simplescalar/bin in your PATH environment variable. Type the following commands: cd sim3 make cd examples make Note that examples/MPLib.o is a tricky SimpleScalar binary file to build and thus has been supplied pre-built. Configuration parameters There are fortunately far fewer configuration options than sim-outorder and you probably can leave them all at the default values (except for number of processors). Parameters are set by using the format -Parameter:value. Run sim3mp by typing: sim3mp parameter-strings program-to-simulate parameters-for-simulated-program Parameter Value type Meaning Default Processors unsigned integer Number of processors 1 StackSize unsigned integer Size of stack on each processor 0x800000 L1-I-Banks unsigned integer L1 I-cache banks 4 L1-I-LineSize unsigned integer L1 I-cache line size (bytes) 128 L1-I-BankSize unsigned integer L1 I-cache bank size (bytes) 32 L1-I-WriteBack boolean L1 I-cache write policy: -back (true) or -through (false) false L1-I-FSB-SC unsigned integer L1 I-cache bus transaction start time (cycles) 0 L1-I-FSB-BS unsigned integer L1 I-cache bus transaction transfer time (cycles) 1 L1-I-Access unsigned integer L1 I-cache extra access time (cycles) 0 L1-D-Banks unsigned integer L1 D-cache banks 2 L1-D-LineSize unsigned integer L1 D-cache line size (bytes) 128 L1-D-BankSize unsigned integer L1 D-cache bank size (bytes) 64 L1-D-WriteBack boolean L1 D-cache write policy: -back (true) or -through (false) false L1-D-FSB-SC unsigned integer L1 D-cache bus transaction start time (cycles) 0 L1-D-FSB-BS unsigned integer L1 D-cache bus transaction transfer time (cycles) 1 L1-D-Access unsigned integer L1 D-cache extra access cycles 0 L2-C-Banks unsigned integer L2 cache banks 4 L2-C-LineSize unsigned integer L2 cache line size (bytes) 128 L2-C-BankSize unsigned integer L2 cache BankSize (bytes) 2048 L2-C-WriteBack boolean L2 cache write policy: -back (true) or -through (false) true L2-C-FSB-SC unsigned integer L2 cache bus transaction start time (cycles) 0 L2-C-FSB-BS unsigned integer L2 cache bus transaction transfer time (cycles) 1 L2-Access unsigned integer L2 cache access time (cycles) 12 SNOOPY-FSB-SC unsigned integer Snooping bus transaction start time (cycles) 4 SNOOPY-FSB-BS unsigned integer Snooping bus transfer time (cycles) 2 DRAM-SC unsigned integer Main memory bus transaction start time (cycles) 60 DRAM-BS unsigned integer Main memory bus transfer time (cycles) 10 DRAM-PageSize unsigned integer Page size (bytes) 4096 OutputFormat integer Output format: human (0) or machine (1) 0 OutputFile string Output filename stdout Modifying sim3mp The first task you will have to perform is to add code to gather statistics on the numbers of cache line state transitions. To this end some of the files you should modify are: DisembodiedSnoopyCache.cxx DisembodiedSnoopyCache.h sim3mp.cxx Simulator.cxx Simulator.h You will either have to make another version of sim3mp which uses your new four state cache coherency protocol or provide a command line option to select between three and four state cache coherency protocols. Either way the intention is to compare the two schemes. Writing multiprocessor programs Use C, not C++. All simulated processors run a copy of the same program, share global variables but have separate stacks and local variables. Be sure to link in the pre-built MPLib.o library found in the examples subdirectory, which replaces some standard system calls with multiprocessor-compatible versions. The Makefile in that subdirectory shows how to do so. synch.c is a trivial multiprocessor example program. Semaphores can be used for more complicated tasks than the simple lock scheme I've implemented. Note that every processor starts executing a copy of the program in a separate process - there is no need to call a fork() system call to initialize the processes on each processor. Download synch.c into the examples subdirectory. Concatenate add-to-makefile to examples/Makefile and build synch.ss with the following commands: cd examples Download add-to-makefile cat add-to-makefile >> Makefile make synch.ss Benchmark programs Unfortunately there's something odd about the way multiprocessor programs are compiled, which messes up the passing of command line options to the simulated binaries. You will have to modify the programs to hardcode in the options before recompiling and simulating them with sim3mp. Concatenate add-to-makefile-2 to examples/Makefile. Download sor.c into the examples subdirectory. Be sure to pass the parameter -Processors: to sim3mp with a value matching the value of the variable NUM_PROCS when running sor.ss. Concatenate add-to-makefile-3 to examples/Makefile. Download quicksort.c and quicksort.h into the examples subdirectory. Be sure to pass the parameter -Processors: to sim3mp with a value matching the value of the variable NUM_PROCS when running quicksort.ss.

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