Reducing Cache Misses with more “Associativity” -- Victim caches
First example (in this course) of an “hardware assist”
Victim cache: Small fully-associative buffer “behind” the L1 cache and “before” the L2 cache
Of course can also exist “behind” L2 and “before” main memory
Main goal: remove some of the conflict misses in L1 direct-mapped caches (or any cache with low associativity)