Conceptual execution on a processor with ILP
Instruction fetch and branch prediction
- Corresponds to IF in simple pipeline
- Complicated by multiple issue and the potential need to fetch more than one basic block at a time
Instruction decode, dependence check, dispatch, issue
- Corresponds (many variations) to ID
- Although instructions are issued (i.e., assigned to functional units), they might not execute right away (cf. reservation stations)
Instruction execution
- Corresponds to EX and/or MEM (with various latencies)
Instruction commit
- Corresponds to WB but more complex because of speculation and out-of-order completion