Example
Load F6, 34(r2) Load f-p register F6
Load F2, 45(r3) Load latency 1 cycle
MulF F0,F2,F4 Mult latency 10 cycles
Sub F8, F6,F2 Add/sub latency 2 cycles
DivF F10,F0,F6 Divide latency 40 cycles
Assume that the 2 Loads have been issued, the first one completed, the second ready to write. The next 3 instructions have been issued (but not dispatched).