Name dependence
Anti dependence Si:
<- R1+ R2;
.; Sj: R1 <-
-
- At the instruction level, this is WAR hazard if instruction j finishes first
Output dependence Si: R1 <-
;
.; Sj: R1 <-
-
- At the instruction level, this is a WAW hazard if instruction j finishes first
In both cases, not really a dependence but a naming problem
- Register renaming (compiler by register allocation, in hardware see later)