CSE 586 Computer ArchitectureLecture 3

4/13/00

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Table of Contents

CSE 586 Computer ArchitectureLecture 3

Highlights from last week

Highlights from last week (c’ed)

Highlights from last week (c’ed)

How to improve (decrease) CPI

Instruction Level parallelism (ILP)

Where can we optimize? (control)

Where can we optimize? (data dependencies)

Compiler optimizations

Data dependencies (RAW)

Loop dependences and optimizations

Loop-level parallelism

Software pipelining

Name dependence

Control dependencies

Static vs. dynamic scheduling

Dynamic scheduling

Issue and Dispatch

Implementations of dynamic scheduling

Scoreboarding -- The example machine(cf. Figure 4.3 in your book)

Scoreboard basic idea

An instruction goes through 5 steps

Execution steps under scoreboard control

Execution steps under scoreboard control (c’ed)

Optimizations and Simplifications

What is needed in the scoreboard

Condition checking and scoreboard setting

Tomasulo’s algorithm

Reservation stations

Tomasulo’s solution to resolve hazards

Example machine (cf. Figure 4.8)

An instruction goes through 3 steps

An instruction goes through 3 steps (c‘ed)

Other checks/possibilities

Conceptual execution on a processor with ILP

Register renaming - Generalities

Register renaming – Scheme 1: File of physical registers

Scheme 1: Example

Register renaming – Scheme 2; Reorder buffer

Scheme 2: Example

Data dependencies with register renaming

More on reorder buffer

Example machine revisited

Need for 4 stages

Need for 4 stages (c’ed)

Author: cselab

Email: baer@cs.washington.edu

Home Page: http://www.cs.washington.edu/education/courses/586

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