Integer pipeline (RISC) precise exceptions

• Recall that exceptions can occur in all stages but WB

• Exceptions must be treated in instruction order

  • Instruction i starts at time t
  • Exception in MEM stage at time t + 3 (treat it first)
  • Instruction i + 1 starts at time t +1
  • Exception in IF stage at time t + 1 (occurs earlier but treat in 2nd)

Previous slide

Next slide

Back to first slide

View graphic version