Intel Pentium
2 integer ALU’s of the 5 stage AGI type (not quite)
- More stages needed for fetch/align and decode (2 1/2 stages)
- AGI = address generation interlock (cf. Golden and Mudge paper)
First 2 stages common to both pipes
F-P unit has 8 stages (including the common 2); latency of 3 cycles.
Branch penalty. If correct prediction in BTB or branch not taken no delay; otherwise 3 or 4 cycles