Branch Target Buffers

• BPT: Tag + Prediction

• BTB: Tag + prediction + next address

• Now we predict and “precompute” branch outcome and target address during IF

  • Of course more costly
  • Can still be associated with cache line (UltraSparc)
  • Implemented in a straightforward way in Pentium; not so straightforward in Pentium Pro (see later)
  • Decoupling (see later) of BPT and BTB in Power PC and PA-8000
  • Entries put in BTB only on taken branches (small benefit)

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