Where to put the BPT
Associated with I-cache lines
- 1 counter/instruction: Alpha 21164
- 2 counters/cache line (1 for every 2 instructions) : UltraSparc
- 1 counter/cache line (AMD K5)
Separate table with cache-like tags
- direct mapped : 512 entries (MIPS R10000), 1K entries (Sparc 64), 2K + BTB (PowerPC 620)
- 4-way set-associative: 256 entries BTB (Pentium)
- 4-way set-associative: 512 entries BTB + “2-level”(Pentium Pro)