Highlights from last week (c’ed)

• ISA (RISC and CISC)

• RISC where R stands for:

  • Restricted (relatively small number of opcodes)
  • Regular (all instructions have same length )
  • And also, few instruction formats and addressing modes

• RISC and load-store architectures are synonymous

• CISC

  • Fewer instructions executed but CPI/instruction is larger
  • More complex to design

• VLIW-EPIC (might talk about it later in the quarter)

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