Table of Contents
CSE 586 Computer Architecture
Highlights from last week
Highlights from last week (c’ed)
Highlights from last week (c’ed)
PPT Slide
Control unit of simple pipeline
Branch statistics
Control hazards (branches)
Better (simple) schemes to handle branches
Simple static predictive schemes
Static schemes (c’ed)
Static schemes (c’ed)
Penalties increase with deeper pipes and multiple issue machines
Dynamic branch prediction
Basic idea
Penalties (Predict/Actual) BPT improves only the T/T case In what’s below the number of stall cycles (bubbles) is for a simple pipe. It would be larger for deeper pipes.
Branch prediction tables and buffers
Simplest design
Variations on BPT design
Improve prediction accuracy (2-bit saturating counter scheme) Property: takes two wrong predictions before it changes T to NT (and vice-versa)
Two bit saturating counters
Where to put the BPT
Performance of BPT’s
Prediction accuracy
Branch Target Buffers
BTB layout
Another Form of Misprediction in BTB
Decoupled BPT and BTB
Decoupled BTB
Correlated or 2-level branch prediction
What should a good predictor do?
General idea: implementation using a global history register and a global PHT
Classification of 2-level (correlated) branch predictors
Two level Global predictors
Two level per-address predictors
Gshare: a popular predictor
Hybrid Predictor (schematic)
Evaluation
Summary: Anatomy of a Branch Predictor
Pentium Pro
Return jump stack
Resume buffer
A sample of recent pipeline configurations
MIPS R4000 pipelines
An illustration of superpipelining
Branch and load delays
MIPS R10000 pipelines
PPT Slide
DEC (now Compaq) Alpha pipelines
PPT Slide
Alpha 21164
IBM Power PC
Intel Pentium
PPT Slide
Pentium Pro
PPT Slide
Control Hazards (c’ed)
Exceptions
Precise exceptions
Precise exceptions (cont’d)
Integer pipeline (RISC) precise exceptions
Treating exceptions in order
Difficulties in less RISCy environments
Extending simple pipeline to multiple pipes
PPT Slide
Hazards in example multiple cycle pipeline
RAW:Example from the book
Conflict in using the WB stage
Example on how to reserve the WB stage
WAW Hazards
Out-of-order completion
Exception handling
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