ISA’s (RISC, CISC, EPIC)
In RISC, R stands for:
- Restricted (relatively small number of opcodes)
- Regular (all instructions have same length )
- And also, few instruction formats and addressing modes
RISC and load-store architectures are synonymous
CISC
- Fewer instructions executed but CPI/instruction is larger
- More complex to design
VLIW-EPIC
- Compiler-based exploitation of ILP